Authors: Safaa S. Omran, Ibrahim A. Amory
Department of Computer Engineering, College of Electrical and Electronic Engineering Techniques
Reconfigurable cache memory is important to improve the cache performance and reduces the energy consumption. In this paper, a review for previous papers related with reconfigurable cache memory were presented and compared it with our work in which we implemented two dimensional reconfigurable cache memory with exploitation of full amount of cache memory size with different organizations and compare the performance of different cache organizations.
Keywords: Reconfigurable Cache; Hit ratio; Energy consumption; SRAM; FPGA.
. Sivarama P. Dandamudi, Fundamentals of Computer Organization and Design.
2nd ed. New York, USA: Springer, 2002.
. D. H. Albonesi, “Selective Cache ways: on demand cache resource allocation,” in
Proc. 32nd International Symposium on Microarchitecture, 1999, pp. 248-259.
. P. Ranganathan, S. Adve, and N. Jouppi. “Reconfigurable Caches and their
Application to Media Processing”. In 27th International Symposium on Computer
Architecture, June 2000.
. C. Zhang, F. Vahid, and W. Najjar, “A highly configurable cache architecture for
embedded systems,” in ISCA, 2003.
. Santana Gil, A.D., Benavides, Hernandez, Herruzo, ”Reconfigurable Cache
implemented on an FPGA” International Conference on Reconfigurable
Computing and FPGAs, IEEE. 2010.
. Karthik T. Sundararajan, Timothy M. Jones and Nigel Topham, “Smart Cache: A
Self Adaptive Cache Architecture for Energy Efficiency”. In International
Conference on Embedded Computer Systems: Architectures, Modeling and
Simulation, IEEE, 2011.
. Liming Chen, Xuecheng Zou, Jianming Lei and Zhenglin Liu, “Dynamically
Reconfigurable Cache for Low-Power Embedded System”. Third International
Conference on Natural Computation, IEEE, 2007.
. C.J. Janraj, T. Kalyan, T. Warrier, M. Mutyam, “Way sharing set associative
cache architecture”, in: 25th International Conference on VLSI Design (VLSID),
2012, pp. 251–256.
. Jungwoo Park, Jongmin Lee and Soontae Kim, “A Way-Filtering-Based Dynamic
Logical–Associative Cache Architecture for Low-Energy Consumption”. In IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, 2017, pp.
793 – 805.
. Bhargavi R. Upadhyay and T S B Sudarshan, “Design Space Exploration of
Cache Memory –A Survey”. In ICEEOT, IEEE, 2016.
. Safaa S. Omran and Ibrahim A. Amory, “Design of Two Dimensional
Reconfigurable Cache memory using FPGA”.In ICEDSA IEEE, UAE, 2016.